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STM32H7RS Power Controller (PWR) Block

So... if you're here from the RCC article, I know I said that this is a quick one, but it's actually a more in-depth topic than I anticipated. Oops...

Rails

Quick note before we start - you will see me throw the term 'rails' around - that's engineer talk for "power line".

A rail is a stable voltage supply that's capable of powering parts of the board on, and multiple rails can coexist at the same time, all powering different stuff.

Regulators & VCORE

Regulators are what control how much voltage the electronics actually receive. The STM32H7RS has 2:

LDOs are linear regulators, meaning they just take the input, get the difference from the target output, and use a variable resistor to regulate how much voltage passes through.

They can take voltage that's similar to the target voltage and output the target voltage, which will power our STM32. For example, running the STM32 at 3.3V from a battery which outputs 3.4V as it begins to run out of charge will still be manageable - the LDO can cover that tiny 0.1V drop.

Note I said drop, the LDO can only decrease the input voltage to the target voltage, not the other way round.

SMPS are the other one.

They work by rapidly switching a transistor on/off at high frequencies as needed.

Which To Use?

In short:

In any case, any combination of these will act as input to the VCAP rail - that's the rail which gets created through the VDD rail, which is what supplies the input to LDO/SMPS.

Alternatively, you can use VCAP as input - this involves disabling/bypassing both LDO and SMPS and powering the board internally yourself.

VCAP

A quick note on the VCAP idea - as I said, it's just a rail which can be used to power things. In the case of STM32, it actually powers the CPU, system logic, EXTI, peripherals, RAM, and other things I probably am not aware of.

So whether you use it as output (activating LDO/SMPS) or input (using your own voltage supply), it feeds into VCORE and powers on the most critical parts of your board.

How To Use Them?

On the STM32H7S3L8, the datasheet outlines the register PWR_CSR2 with the following (relevant) bits:

The hardware is protected from writing invalid combinations - it just ignores the write. You can see the invalid combinations on the datasheet (table 44 for the H7S3L8).

NOTE! You can only write to this register once per power cycle (you need a full power-off to write to it again), and writes should happen as soon as possible after power on.

The Power-On Sequence

When the board receives power after a power-on reset:

  1. VDD is monitored until it's stable
  2. Once it's stable, LDO and SMPS are enabled
  3. Those two create VCORE, but the system must remain in reset until VCORE is stable
  4. Once it's stable, the system exits reset and the HSI clock is enabled as a result
  5. Boot sequence is as standard from then on - read 0x00000000, set MSP, read Reset Handler address from 0x00000004, etc.

Other Rails

VDD Rail

This is the rail which powers the board's I/O and analog blocks - the analog blocks that are required for the rest of the board to work (oscillators, power modes, and reset detection circuitry - VCORE can't power those)

VBAT Rail

Typically, this means Voltage BATtery, but it can also be a supercapacitor.

This is used when VDD drops below a certain threshold, usually meaning it has been turned off. The switch from VDD to VBAT (and back) is handled by hardware automatically.

Just note that it doesn't take over VCORE - things like CPU, peripherals, EXTI, etc. go offline untill VDD is reinstated. The purpose of VBAT is just to keep a backup domain (see that section) alive in between power cycles, such as Real-Time Clock (RTC), backup RTC registers, and backup SRAM.

VBAT has 2 'subparts', which may or may not be specific to the H7RS family, so double check your datasheet:

VDDXSPI1 And VDDXSPI2

These two rails are for powering dedicated XSPI-related peripherals, which is typically external flash memory.

VDDA and VSSA

VDDA is for analog peripherals, which are sensitive to the noise on the standard VDD line.

It's is the same voltage as VDD - in fact it's usually derived from VDD - but VDDA undergoes filtering to make it less noisy.

VSSA is the ground-equivalent for whatever VDDA is plugged into.

VDD33USB And VDD50USB

VDD33USB is another rail, the 33 meaning it's 3.3V. It can either be powered on by the onboard regulator from VDD50USB (5.0V supply, usually USB cable from a computer), or externally by directly getting connected.

As this is USB-related, there's one other quirk - high-speed (HS) USB. There's a pin, DVDD, which the spec outlines must be connected to ground if HS isn't used, otherwise it needs to get connected to VDD. This is to avoid floating lines on the DVDD pin if HS isn't used - which can cause unpredictable behaviour.

Backup Domain

Normally, this part gets powered by VDD, but if its voltage dips too low (e.g. it's powered off), VBAT takes over automatically through a hardware power switcher.

The backup domain contains these things:

Power Supply Monitoring

These prevent the board from functioning outside of normal voltage, which prevents unpredictable behaviour.

There are multiple monitoring systems on the STM32H7RS.

Reset Events

The following trigger a reset when they act:

* A reset state is when the CPU is prevented from executing code.

Interrupt Events

The following fire an interrupt when they act:

Tamper Events

The word 'tamper' is a bit unclear - it's not actually someone messing with the hardware/software, it'll become clear in the Power Modes section lower down the page:

* This detector can only be enabled when the system is powered by the direct (on-board) SMPS regulator only.

Other Monitors

There are also 3 extra monitors briefly mentioned in the STM32H7RS PWR PowerPoint, so I'll just bring them up here for completion, as they can all generate status bits to indicate they're ready to use, not that there's a voltage issue:

All 3 have relevant bits in the PWR_CSR1 and PWR_CSR2 registers to indicate when they are ready.

Power Modes

STM32s have different power modes that the voltage regulator implements:

The main difference between them is mainly how much voltage VCORE is receiving (if any), and thus whether the oscillators, clocks, and voltage regulator are on or not, and the core idea I've gathered is that the different modes go in this order, ranked by capability: RUN, SLEEP, STOP, STANDBY.

RUN mode gives full voltage to VCORE and operations are as normal.

SLEEP is a slightly odd one - it's basically RUN, but the CPU clock is off, so code execution is disabled, and peripheral clocks can be optionally disabled. Usually used with peripheral clocks on to keep the peripherals active but suspend CPU while it waits for something like an external interrupt. Note that this does include the on-board peripherals like NVIC and SysTick, which generate interrupts.

Also, in SLEEP mode, I/O pins keep the same state as in RUN mode.

STOP provides enough voltage to VCORE (called a retention value) to keep the registers and memory preserved, though peripheral clocks can be kept on. This is very power efficient, and the MCU can be woken up by external interrupts and the Real-Time Clock.

This mode also lets peripherals send a kernel clock activation request - e.g. over UART, where the peripheral sends a specific UART message, and if it's correct, the kernel clock turns on and the system returns to RUN mode, otherwise the clock turns off and we stay in STOP mode.

You can also program the system to keep flash memory in a low-power mode via PWR_CR1, which will make getting back on track faster after a wake-up.

A cool little quirk here is that if flash memory is being programmed as you enter STOP mode, STOP mode will actually get delayed until the programming is finished so you don't have a half-complete image.

There's a complete list of what can be kept on in SLEEP mode on the STM32H7RS PWR PowerPoint, page 24. It's mostly oscillator/clock stuff.

STANDBY powers VCORE down. Realistically, only the backup SRAM and RTC remain powered and retain data via VBAT. At first, this sounded like a power-off with the extra step of VBAT, but you can actually wake the board up again via the WKUP pin, RTC alarms, tamper event (remember how I called the temperature and battery voltage threshold detectors 'tamper' events?), NRST pin (though that triggers a hardware reset, not a wake-up), or a watchdog reset. Once a wake-up happens, the system is back to running from the HSI oscillator

Those aren't all possible ways of waking up from STANDBY, but they're the main ones I found in my sources.

Besides that, there is also some misc. info on STANDBY mode:

* The reason it's called high-impedance is actually interesting. You can think of impedance as meaning resistance, which changes the term to "high-resistance". Take a look at this image - when a pin is disconnected, both transistors between the pin and Vcc/Gnd do not allow current to flow. STM32's pins use what's called CMOS transistors, which increase the resistance to near infinity when the transistor gate is closed. So, when a pin is disconnected, both transistors connected to it are in a near-infinite resistance state, hence high-impedance. Fun but kind-of-useless fact for most cases.

Dynamic Voltage Scaling

This topic felt like a sub-section of Power Modes at first, but the core idea warrants its own section. As the name implies, this is voltage scaling that dynamically changes on-demand, and it's automatic - perfect for power consumption optimisation.

Also, it seems like a feature exclusive to the H7RS chips, which is what this article is for!

It works by exploiting the fact that as clock frequencies and operational voltage go up, so does the power consumption. And that's exactly what happens - the main regulator which supplies VCORE can be adjusted according to the board's maximum operational frequency (irregardless of whether LDO or SMPS is used - both can provide 2 different voltages), and there are some extra things I'll mention if VCAP is bypassed and VCORE is powered externally.

VOS And SVOS

These stand for VOltage Scaling and STOP VOltage Scaling respectively, and yes that's STOP like the STOP power mode. They each have 2 modes: low and high.

Thankfully, the management principles for the STM32H7 are simple (thank you STMicroelectronics):

Frequency/VOS Table

I keep referencing it, but the STM32H7RS PWR PowerPoint has been my main source for the article so far - it's literally made by ST themselves and so it's detailed enough as a standalone source for most parts.

Anyway, enough praising... if you go to it (on page 19), there's a table which outlines how high of a frequency you can get with VOS high and VOS low with different temperatures and ECC settings - ECC is Error Correction Code, something available on H5, H7, U3, U5, and C3 series STM32s, which can detect and potentially correct bit-errors in flash/RAM.

VOS In Power Modes

Now that we have VOS under our toolbelt, here is some extra info!

STOP

So I already mentioned the system can switch between power modes - namely RUN and STOP for this next part.

When entering STOP mode, you can actually preselect which SVOS level you want to use in the PWR_CR1 register - I'll leave you to look at your specific datasheet for that. Also, the system can switch between SVOS high and SVOS low in SLEEP mode as needed.

STOP mode also sets the voltage regulator into low-power mode as it doesn't need its full power.

Obviously, what SVOS selects will depend on the idle power consumption:

If the MCU is in SVOS high while in STOP mode, peripherals using the LSI/LSE clocks can also continue operating besides peripherals with kernel clock request capabilities.

SLEEP

Only one real note here, and it's the same as STOP mode - voltage regulators remain active and can switch between VOS high and VOS low.

STANDBY

Also only one note here - when exiting STANDBY (and STOP as well), the system goes into a VOS low RUN state.

Low-Power Monitoring Pins

GPIOA pins 5 and 6 can be used to track power mode transitions when configured with PWR_CSLEEP and PWR_CDSLEEP.

Here's a table to summarise the pin values: | CSLEEP | CDSLEEP | Power Mode | | :----: | :-----: | :--------: | | 0 | 0 | RUN | | 1 | 0 | SLEEP | | 0 | 1 | RUN | | 1 | 1 | STOP |

You'll notice a distinct lack of indication for SUSPEND mode - that's because in SUSPEND, VCORE is unpowered, which is what generates the CSLEEP and CDSLEEP signals.

VBAT Mode

I talked about both VBAT and the backup domain separately, but here's how they work together.

First, a hardware power switch toggles between VDD and VBAT automatically when VDD stoops below a voltage threshold, and back when it's above the threshold.

When VBAT is powering the backup domain (hence, VDD and most likely VCORE are off), only the Low-Speed External (LSE) oscillator is on. As a result, the Real-Time Clock (RTC) can also be on due to the LSE being able to clock it.

One channel of the ADC2 (Analog-to-Digital Converter) gets dedicated to monitoring the external VBAT supply pin.

I'm yet to write an article on the ADC (frankly because I don't know enough to write anything worthwhile), but essentially it can turn continuous data (VBAT input voltage in this case) and turn it into discrete data that can be represented as 1’s and 0’s and used by the system.

If you look into the PWR_BDCR register for a bit called VBE, you'll also find out you can charge the battery supply. It's automatically disabled, but when on and VDD is present, the battery can be charged.

Interrupts

There's only one relevant PWR interrupt (talking about the PWR block itself, not things like RTC or WKUPx pins) - and that's the PVD interrupt.

PVD (Power Voltage Detector) monitors VDD and VDDA, and if it detects a voltage outside of the set thresholds (you set them in PWR_CR1), it raises the PVDO bit in PWR_SR1 and generates an interrupt request*.

If this happens, SLEEP and STOP modes are also automatically exited, but STANDBY mode isn't exited from what I could tell (most likely because VCORE isn't running to power EXTI, genius...).

* There is also 'AVD' which is for analog signals. It has the equivalents of threshold bits in PWR_CR1 and an AVDO status bit in PWR_SR1, but the STM32H7RS HAL drivers don't seem to mention it - maybe I'm wrong and didn't dig around enough, so if you know something I don't, let me know! But besides that, just be aware if you plan on using analog signals for interrupts on the PWR block and you're using the HAL.

Option Bits

These are bits which you write into the flash memory to signal a permanent change to the system.

Here are the relevant ones for the PWR block:

Sources

STMicroelectronics - STM32H7RS Power Controller Texas Instruments - Understanding Low Drop Out (LDO) Regulators STM32 Standby Mode & Wakeup Pins/Sources How to wake up an STM32 microcontroller from low-power mode with the USART or the LPUART Tri-state buffer, why is it called high-impedance?